In recent years, a register window system has been suggested as a configuration of general-purpose registers used in information processing apparatuses. This aims at provision of plural register sets (windows) in order to eliminate the need to save and restore information between registers and memory devices, which results when subroutines are called or returned.
However, when an immense number of windows are used, data cannot be read from a register onto an execution unit at high speed, which is problematic. In order to cope with this problem, a method is suggested in which a window that is currently referred to among general-purpose registers is held as a work register and this work register is made to operate as if it is cache memory in order to reduce time loss in reading or writing information that might result, depending upon size.
However, a configuration in which only 1 window that is being referred to currently is held as a work register requires that data be transferred to the work register each time the window is switched. Because data that should be referred to during the transfer does not exist, subsequent instructions cannot be executed until the data transfer is terminated.
This configuration results in severe degradation in performance of information processing apparatuses in which a large number of simultaneous instructions are issued using an out-of-order instruction execution method, wherein the order of executing instructions is changed so that execution of instructions starts from those that have become ready to be executed regardless of the execution order in the program.
Accordingly, in information processing apparatuses using an out-of-order instruction execution method, a large number of instructions are stored in a buffer and are executable instructions; such instructions are executed after changing the execution order that was specified by the program so that the throughput of the instructions is improved.
However, in the above configuration, the execution order of instructions cannot be changed before or after window switching, and thus executions of all instructions stored subsequently to the switching are required to wait, and this prevents an out-of-order execution method from functioning.
Patent Document 1 proposed a method in which plural windows are held as a work register in order to solve the above problem. Using this method, windows adjacent to the window that is being referred to are held as a work register set, and thereby subsequent instructions can be executed without waiting for data transfer when windows are switched successively.
Also, it is generally known that recent information processing apparatuses adopt a superscalar method, by which processes of computations are parallelized as much as possible so as to increase efficiency in using respective execution units so that all aspects of the performance are improved.
However, not all execution units operate in an information processing apparatus adopting a superscalar method, and there is a problem in that the parallelism is not fully utilized. Thus, Simultaneous MultiThreading (SMT) is suggested as a method by which resources (peripheral circuits such as computing units and data transfer buses) that are not fully utilized by a single thread can be distributed to plural threads so that the inherent parallelism of an information processing apparatus can be utilized at a maximum.
As a solution to realization of SMT, it is conceivable to simply increase the number of resources in accord with the number of threads. This means that 2 SMTs are configured using twice as many resources as a single thread. In such a case, there is no conflict between threads that are accessing the same resources. However, an increase in the number of threads immensely increases the number of necessary resources, which reduces efficiency in using such resources. This works against the inherent purpose of SMT.
In this situation, a configuration is required in which resources are partially commoditized so that an increase in the number of resources can be suppressed and the efficiency in using such resources can be increased. Also, partial commoditization of resources causes a problem in which a conflict between different threads accessing common resources interferes with instruction executions in other threads.
Patent Document 1: Japanese Laid-open Patent Publication No. 2003-196086